Flip-flops are one of the fundamental circuit blocks used by digital circuit designers. The term flip-flop refers, genetically, to a device that receives either a logic high or logic low state as an input and saves the input for use at some later time. Typically, a flip-flop samples and saves its input at a time indicated by a clocking signal. Otherwise, the ignores the logic state at its input. Flip-flops are generally the simplest example of a binary memory circuit.
Flip-flops are often used in applications where signal propagation delays are critical. For instance, a phase locked loop (hereafter simply "PLL") is a device that synchronizes an output clock signal to a master or "input clock signal in both phase and frequency. The output clock signal is fed back to an input of the PLL where the phase and frequency of the output clock signal are continuously compared to the phase and frequency of the master clock signal. Therefore, a PLL generates an output clock signal slaved to a master clock signal. A PLL may be modified to generate an output clock signal whose frequency is a particular ratio of the frequency of the input clock signal. Such a circuit is useful in data processors that use an internal clock signal that has a higher frequency than the frequency of an input bus clock signal. A designer may control the ratio of the bus and internal clock frequencies by inserting a circuit reduces the frequency of the signal in the PLL feedback loop by a certain factor, typically, two, four, six, eight, etc. The PLL synchronizes the input clock signal and the "reduced frequency" clock output. Therefore, the input to the frequency reducing circuit is two, four, six, eight times, etc., greater than the frequency of the input clock signal. The input to the frequency reducing circuit is then used as the "output" of the PLL.
Flip-flops are often used to build the frequency reducing circuit described above. Unfortunately, a frequency reducing circuit incorporating a flip-flop introduces delay into the feedback loop of the PLL, This delay causes the two clock signals to become misaligned with respect to phase if the input of the frequency reducing circuit generates the output of the PLL. In some applications this delay may be unacceptable, Also, this delay may be so small that it may not be possible to model the delay prior to circuit manufacture with enough accuracy to design a delay matching circuit.